(a) Field of the Invention
The invention relates to an electronic device, particularly to a clock generation device and method thereof.
(b) Description of the Related Art
In an N-channel time-interleaved analog-to-digital converter, “N” (N is a positive integer) analog-to-digital converters are connected in parallel to form N channels to increase the sampling rate of the analog-to-digital converter by N times. However, a time-interleaved analog-to-digital converter still has non-ideal problems, such as sampling timing mismatch between the N analog-to-digital converters (i.e., sampling timing skew) or gain mismatch and offset mismatch between the N analog-to-digital converters.
Sampling timing mismatch is due to different sampling cycles of the channels of analog-to-digital converters. For example, as shown in FIG. 1A, an analog-to-digital converter with a sampling rate of 1 GHz comprises M analog-to-digital converters ADC1, ADC2˜ADCM (the number of ADC is M), with a sampling rate of 250 MHz. For now, four analog-to-digital converters are used as an example (M=4). When the analog-to-digital converter ADC1 finishes signal sampling, the analog-to-digital converter ADC2 starts sampling after a first interval of 1/1 GHz (that is, 1 ns) has elapsed. Then, the analog-to-digital converter ADC3 starts sampling after the analog-to-digital converter ADC2 finishes signal sampling and a second interval of 1/1 GHz (that is, 1 ns) has elapsed. Likewise, the signals shown on the right-hand side of FIG. 1A are generated. Practically, the sampling timing between channels of the analog-to-digital converters cannot be set to a 1-ns interval accurately, resulting in sampling timing mismatch of N analog-to-digital converters.
Sampling timing mismatch is caused by different signal path lengths of the signal sources of the analog-to-digital converters and an asymmetric circuit configuration. For example, a conventional non-overlapping clock generator is shown in FIG. 1B. The non-overlapping clock generator generates clocks CK1 and CK2 as the clock sources of a 2-channel time-interleaved analog-to-digital converter. The following problems may occur.
At first, clocks CK1 and CK2 are generated through a path marked by the bold faced arrow, in order to produce non-overlapping clocks. Since the path from the clock CLKin to the clock CK1 and the path from the clock CLKin to the clock CK2 cannot be too short and there are physical limitations in chip fabrication to fabricate exactly the same elements, the mismatch between the path from the clock CLKin to the clock CK1 and the path from the clock CLKin to the clock CK2 causes the 2-channel time-interleaved analog-to-digital converter to have sampling timing mismatch to reduce circuitry performance. Moreover, even though the physical limitations in chip fabrication is disregarded, as shown in FIG. 1B, the configuration of the clock generation circuit is asymmetric and thus the interval between providing the clock CLKin and generating the clock CK1 is different from that between providing the clock CLKin and generating the clock CK2.